PDN target impedance, and the caps to meet it.
The impedance your power rail must stay under, the bulk capacitance below the regulator, and roughly how many decaps above it.
PDN target impedance calculator
- Target impedance
- 3 mΩ
- Bulk capacitance below the regulator hand-off
- 530.5 µF
- Decaps needed up to 100 MHz
- 105in parallel, by mounted inductance
Flat-target estimate. Plane resonances and anti-resonances between capacitor values need a full PDN model.
What is PDN target impedance?
PDN target impedance is the highest impedance the power distribution network may present to a load if the supply voltage is to stay within tolerance during a current step. It is Z_target = V × ripple / ΔI: a 1.0 V rail with a 3 % ripple budget and a 10 A transient gives 3 mΩ. Designers then keep the impedance seen by the load below that line from DC up to the highest frequency the load draws current at. The voltage regulator holds it at low frequency, bulk capacitors take over above the regulator’s bandwidth, and ceramic decoupling capacitors cover the higher frequencies, where their mounted inductance, not their capacitance, sets how many you need. This calculator gives the target, the bulk capacitance needed at the regulator hand-off, and an estimate of how many decoupling capacitors in parallel keep the impedance under target.
Worked example
Three rails, 100 kHz regulator hand-off, 0.5 nH mounted inductance per capacitor:
| 1 V, 3 %, 10 A | Z_t = 3 mΩ, bulk ≥ 530.5 µF at 100 kHz, 105 caps to 100 MHz |
|---|---|
| 0.8 V, 3 %, 30 A | Z_t = 800 µΩ, bulk ≥ 1.989 mF at 100 kHz, 393 caps to 100 MHz |
| 3.3 V, 5 %, 2 A | Z_t = 82.5 mΩ, bulk ≥ 19.29 µF at 100 kHz, 4 caps to 100 MHz |
When you need the full simulator
This calculator is free to use and answers one question at a time. The full AirInduct Sim simulator goes further:
- Z(f) at the load with the plane-pair cavity, capacitor ESR/ESL and via mounting.
- Anti-resonances between capacitor values shown against the target line.
- A decap optimiser that meets the target with fewer parts.
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Frequently asked questions
What ripple percentage should I use?
Use the share of the rail tolerance you can give to transient droop. Processor and FPGA rails are often specified at ±3 % to ±5 % in total, and part of that is used by regulator set-point error and DC drop, so the transient budget is usually smaller.
Why does mounted inductance matter more than capacitance?
Above its self-resonant frequency a capacitor behaves like its mounting inductance (pads, vias and planes), typically a few hundred picohenries to about 1 nH. The impedance there is 2πfL, so you meet the target at high frequency by putting enough capacitors in parallel to bring the combined inductance down.
Is a flat target impedance enough?
It is a good first pass, but anti-resonances between capacitor values and plane-pair cavity resonances can push the impedance over the target. The PDN & Power Integrity module models them and optimises the capacitor choice.